1. Field of the Invention
The present invention relates mainly to a long distance, ultra high speed optical communication receiver circuit.
2. Description of the Related Art
In recent years, with prevailing network usage there has been increasing demand to increasing the bandwidth of optical communication networks. Since the optical communication network is used for trunk lines, et cetera, it must be capable of long distance communication and of wide band, high speed communication. By conventional methods, however, it has been said that there is only a limited possibility of widening the bandwidth due to the influences of wavelength dispersion, nonlinear effects, et cetera, of optical fiber. In order to solve the problem, an attempt has been proposed for increasing the bandwidth by devising a modulation method for an optical signal, in lieu of a method for suppressing such physical effects directly. In such a proposal, the method for use as a modulation method for the optical signal is the DQPSK (Differential Quadrature Phase Shift Keying) modulation scheme. Note that the present invention, while exemplifying the case of the DQPSK modulation scheme in the following description, is applicable likewise to a case of an M-ary DPSK modulation scheme (where M is 4 or greater).
FIG. 1 shows a configuration of a conventional DQPSK receiver circuit.
This configuration is described in the patent document 1. The DQPSK optical receiver directs the split light to pass through a π/4 delay interferometer 2 and a −π/4 delay interferometer 3, respectively, followed by balanced photodiodes 4-1 and 4-2, respectively, to detect “1” and “0” states of the signal (N.B.: this detection is carried out for Data 1 and Data 2 systems respectively). The detected Data 1 and Data 2 are processed by a logic process unit 9 to restore the original signal.
A DQPSK signal uses phases of light, i.e., π/4, 3π/4, −π/4 and −3π/4, as relative phase values for a signal one symbol prior. The π/4 delay interferometer 2 and −π/4 delay interferometer 3 bi-split the input optical signal, provide one optical signal a delay of one symbol and provide the other optical signal a phase shift of either π/4 or −π/4. By so doing, a balanced photodiode 4-1 of the Data 1 system where the π/4 delay interferometer 2 is equipped receives the phase shifts of π/4 and −3π/4 of the optical signal being converted into intensity changes. Likewise, a balanced photodiode 4-2 of the Data 2 system where the −π/4 delay interferometer 3 is equipped receives the phase shifts of −π/4 and 3π/4 of the optical signal, which are the orthogonal components of the optical signal π/4 and −3π/4, being converted into intensity changes. The logic process unit 9 applies logic processing, such as sequence changes of the Data 1 and Data 2 systems, et cetera, to the signals converted into electric signals by the balanced photodiodes 4-1 and 4-2, thereby restoring the original signals.
[Patent document 1] United States Patent Application Publication No. 2004/0081470
In the conventional circuit, a D-flip flop is equipped at the input to the logic process unit 9 for signals of Data 1 and Data 2 to identify logic values “1” and “0” of the electric signals of the Data 1 and Data 2 systems. If there is a difference in path lengths from the splitter 1 to the logic process unit 9, et cetera, between the Data 1 and Data 2 systems, the phases of input data to the logic process unit 9 of the Data 1 and Data 2 systems become different, the clock identifier phases of the Data 1 and Data 2 systems become shifted if the identification is carried out by using the same clock, resulting in a degrading of the receiving sensitivity. Especially in the domain of 20 GB/sec and above, where the DQPSK modulation scheme is used, a phase difference on the order of picoseconds cannot be tolerated, thus presenting a significant barrier to accomplishing a DQPSK receiver circuit.
As such, the conventional example is not capable of establishing optimum identifier phases for both the Data 1 and Data 2 systems, and further the logic process unit 9 sometimes misidentifies a signal because the Data phases of the two systems are not synchronized, hence it is not possible to obtain a high performance DQPSK receiver.